Reduction in power consumption and cost reduction is key issue for a storage device. For example, reduction in the number of used DRAM memories makes a huge contribution to the reduction in power consumption, cost, and footprint. Recently, SoC LSI equipped with multiple CPUs has been developed. In general, each of the multiple CPUs needs a main memory, respectively. Sharing the multiple CPU memories with other DRAM memories on the LSI can reduce the number of DRAM memories used as the main memories.
FIG. 1 shows an ASIC having a DRAM memory shared between access from a CPU (CPU access) and data flow transfers, and an arbiter enabling the sharing of the memory. In this shared memory configuration, a data buffer for data flows and a main memory of the CPU share the same DRAM memory chip. In the shared memory, usable areas of one DRAM memory are physically separated from each other.
Firmware using a CPU controls hardware such as a data-flow ASIC to transfer data to and from recording media. Since the body of code of the firmware is placed in a main memory, access to the main memory occurs in the operation of the firmware. A delay from when an access request to the main memory is issued until completion of the request is a latency time of the CPU. The longer this latency time, the lower the performance of the CPU.
In this method, if respective data transfers get stuck, this ends up an interruption of a host transfer or reduction in media transfer performance. If the architecture of a data buffer is contemplated, requirements for necessary bands upon simultaneous occurrence of data transfer requests from all blocks need to be satisfied, respectively. Even if a memory is shared between the main memory and the data buffer, the throughput of data flow transfers and CPU access needs to be satisfied. Particularly, when the device is equipped with multiple CPUs, the bandwidth of the DRAM memory needs to be secured. However, the physical band of the DRAM memory, which is decided based on the bus width and frequency, is limited.
Further, the turn around time of a main memory access affects the performance of the CPU. If a request for access to the main memory comes during a transfer other than the main memory access (e.g., data flow transfer), the request will need to wait until completion of the current transfer. Thus, when a memory is shared between the main memory and another DRAM memory, the following problems arise.
1. How to guarantee a required bandwidth of main memory accesses for multiple CPUs within a limited bandwidth. An easy way to ensure the required bandwidth is to increase the physical bandwidth. However, widening the bus width to increase the bandwidth leads to an increase in the number of chips used, and this defeats the intended purpose of reducing the number of memory parts. On the other hand, raising the operating frequency leads to an increase in power consumption, and this is not a perfect solution.
Reducing transfer overhead is effective to improve the bandwidth within a given physical bandwidth. In DRAM technology commonly used, such as DDR3 SDRAM, if the burst transfer length increases by one access, the ratio of overhead can be reduced. In a memory architecture that satisfies the required bandwidth, it is effective to give a long burst transfer length for blocks with high required bandwidth and a short burst transfer length for blocks with low required bandwidth. Data buffer of IBM tape drives is designed based on this concept, achieving relatively low operating frequency with high data transfer efficiencies.
However, in the case of main memory accesses for which the turn around time is a key issue, if memory access is being performed by another block when a main memory request comes, the main memory access needs to wait until completion of the current transfer. It is a possible option to resolve this issue to interrupt the current transfer and allow the main memory transfer, but this cannot be employed in a system with high performance required because this degrades the other blocks' bandwidth.
The overhead in DRAM technology includes a mode register set command (MRS), a command to activate a row address to be accessed (Activate), a command to close the row used (Precharge), a refresh command (Refresh), and others. In accordance with these commands, no data is transferred. Applying the specifications, there is an existing technique not to issue a Precharge command to accesses with consecutive addresses. This is effective for a DRAM exclusively used as a main memory, and this actually leads to overhead reduction. However, in the case of a memory shared among CPUs used for different purposes, this method is not effective because the memory is used by dividing the physical area of the memory and hence the addresses are not consecutive.
The access from a CPU to a main memory is an access in bytes or by a cache line. In the case of a CPU in a built-in system, the cache line is 32 bytes or 64 bytes. In this case, if the data bus for the DRAM memory is 32 bits, the transfer will be in eight bursts or 16 bursts. Thus, the CPU access is not efficient in terms of burst transfer, increasing the overhead.
2. How to reduce turn around time of main memory requests
As mentioned in the above problem 1, if a request for access to the main memory comes during a transfer of another block (e.g., data flow), the main memory request needs to wait until completion of the current transfer. In the case of an arbiter designed to assign the highest priority to the main memory access, the access is allowed to transfer data. The transfer cycle of any other block is at least about 20 clocks on the DRAM memory clock, and this is one of main factors to increase the latency of the main memory access. The method of interrupting the transfer of another block needs to consider a system to compensate for the interruption penalty. To this end, since a retransfer cycle is required, then the transfer overhead increases, making it difficult to guarantee the bandwidth of the block.
Patent Document 1 relates to a bus access arbitration system for data buffer accesses between a host side and a CD media side. When controlling accesses of multiple blocks in a CD drive to a data buffer, this bus access arbitration system puts priorities to accesses from respective blocks and restrictions on the number of accesses therefrom.